Chipmakers proceed to claw for each spare nanometer to proceed cutting down circuits, however a expertise involving issues which are a lot larger—tons of or 1000’s of nanometers throughout—might be simply as vital over the following 5 years.
Known as hybrid bonding, that expertise stacks two or extra chips atop each other in the identical bundle. That permits chipmakers to extend the variety of transistors of their processors and recollections regardless of a common slowdown within the shrinking of transistors, which as soon as drove Moore’s Legislation. On the
IEEE Digital Elements and Know-how Convention (ECTC) this previous Might in Denver, analysis teams from around the globe unveiled a wide range of hard-fought enhancements to the expertise, with just a few exhibiting outcomes that might result in a report density of connections between 3D stacked chips: some 7 million hyperlinks per sq. millimeter of silicon.
All these connections are wanted due to the brand new nature of progress in
semiconductors, Intel’s Yi Shi instructed engineers at ECTC. Moore’s Legislation is now ruled by an idea known as system expertise co-optimization, or STCO, whereby a chip’s capabilities, similar to cache reminiscence, enter/output, and logic, are fabricated individually utilizing the most effective manufacturing expertise for every. Hybrid bonding and different superior packaging tech can then be used to assemble these subsystems in order that they work each bit in addition to a single piece of silicon. However that may occur solely when there’s a excessive density of connections that may shuttle bits between the separate items of silicon with little delay or power consumption.
Out of all of the advanced-packaging applied sciences, hybrid bonding offers the very best density of vertical connections. Consequently, it’s the quickest rising phase of the advanced-packaging trade, says
Gabriella Pereira, expertise and market analyst at Yole Group. The general market is ready to greater than triple to US $38 billion by 2029, in line with Yole, which initiatives that hybrid bonding will make up about half the market by then, though right this moment it’s only a small portion.
In hybrid bonding, copper pads are constructed on the highest face of every chip. The copper is surrounded by insulation, normally silicon oxide, and the pads themselves are barely recessed from the floor of the insulation. After the oxide is chemically modified, the 2 chips are then pressed collectively face-to-face, in order that the recessed pads on every align. This sandwich is then slowly heated, inflicting the copper to increase throughout the hole and fuse, connecting the 2 chips.
Hybrid bonding can both connect particular person chips of 1 measurement to a wafer filled with chips of a bigger measurement or bond two full wafers of chips of the identical measurement. Thanks partially to its use in digital camera chips, the latter course of is extra mature than the previous, Pereira says. For instance, engineers on the European microelectronics-research institute
Imec have created a number of the most dense wafer-on-wafer bonds ever, with a bond-to-bond distance (or pitch) of simply 400 nanometers. However Imec managed solely a 2-micrometer pitch for chip-on-wafer bonding.
The latter is a large enchancment over the superior 3D chips in manufacturing right this moment, which have connections about 9 μm aside. And it’s a fair larger leap over the predecessor expertise: “microbumps” of solder, which have pitches within the tens of micrometers.
“With the gear out there, it’s simpler to align wafer to wafer than chip to wafer. Most processes for microelectronics are made for [full] wafers,” says
Jean-Charles Souriau, scientific chief in integration and packaging on the French analysis group CEA Leti. However it’s chip-on-wafer (or die-to-wafer) that’s making a splash in high-end processors similar to these from AMD, the place the approach is used to assemble compute cores and cache reminiscence in its superior CPUs and AI accelerators.
In pushing for tighter and tighter pitches for each situations, researchers are centered on making surfaces flatter, getting sure wafers to stay collectively higher, and reducing the time and complexity of the entire course of. Getting it proper may revolutionize how chips are designed.
WoW, These Are Some Tight Pitches
The current wafer-on-wafer (WoW) analysis that achieved the tightest pitches—from 360 nm to 500 nm—concerned loads of effort on one factor: flatness. To bond two wafers along with 100-nm-level accuracy, the entire wafer needs to be practically completely flat. If it’s bowed or warped to the slightest diploma, entire sections received’t join.
Flattening wafers is the job of a course of known as chemical mechanical planarization, or CMP. It’s important to chipmaking usually, particularly for producing the layers of interconnects above the
transistors.
“CMP is a key parameter we’ve got to regulate for hybrid bonding,” says Souriau. The outcomes introduced at ECTC present CMP being taken to a different stage, not simply flattening throughout the wafer however decreasing mere nanometers of roundness on the insulation between the copper pads to make sure higher connections.
“It’s troublesome to say what the restrict can be. Issues are shifting very quick.” —Jean-Charles Souriau, CEA Leti
Different researchers centered on making certain these flattened elements stick collectively strongly sufficient. They did so by experimenting with totally different floor supplies similar to silicon carbonitride as an alternative of silicon oxide and through the use of totally different schemes to chemically activate the floor. Initially, when wafers or dies are pressed collectively, they’re held in place with comparatively weak hydrogen bonds, and the priority is whether or not every part will keep in place throughout additional processing steps. After attachment, wafers and chips are then heated slowly, in a course of known as annealing, to type stronger chemical bonds. Simply how sturdy these bonds are—and even the way to determine that out—was the topic of a lot of the analysis introduced at ECTC.
A part of that closing bond power comes from the copper connections. The annealing step expands the copper throughout the hole to type a conductive bridge. Controlling the scale of that hole is vital, explains Samsung’s
Seung Ho Hahn. Too little enlargement, and the copper received’t fuse. An excessive amount of, and the wafers can be pushed aside. It’s a matter of nanometers, and Hahn reported analysis on a brand new chemical course of that he hopes to make use of to get it good by etching away the copper a single atomic layer at a time.
The standard of the connection counts, too. The metals in chip interconnects usually are not a single crystal; as an alternative they’re made up of many grains, crystals oriented in several instructions. Even after the copper expands, the steel’s grain boundaries usually don’t cross from one aspect to a different. Such a crossing ought to scale back a connection’s electrical resistance and increase its reliability. Researchers at Tohoku College in Japan reported a brand new metallurgical scheme that might lastly generate giant, single grains of copper that cross the boundary. “It is a drastic change,” says
Takafumi Fukushima, an affiliate professor at Tohoku. “We at the moment are analyzing what underlies it.”
Different experiments mentioned at ECTC centered on streamlining the bonding course of. A number of sought to scale back the annealing temperature wanted to type bonds—sometimes round 300 °C—as to reduce any danger of injury to the chips from the extended heating. Researchers from
Utilized Supplies introduced progress on a way to radically scale back the time wanted for annealing—from hours to only 5 minutes.
CoWs That Are Excellent within the Discipline
Imec used plasma etching to cube up chips and provides them chamfered corners. The approach relieves mechanical stress that might intrude with bonding.Imec
Chip-on-wafer (CoW) hybrid bonding is extra helpful to makers of superior CPUs and GPUs for the time being: It permits chipmakers to stack
chiplets of various sizes and to check every chip earlier than it’s sure to a different, making certain that they aren’t dooming an costly CPU with a single flawed half.
However CoW comes with the entire difficulties of WoW and fewer of the choices to alleviate them. For instance, CMP is designed to flatten wafers, not particular person dies. As soon as dies have been minimize from their supply wafer and examined, there’s much less that may be executed to enhance their readiness for bonding.
However, researchers at
Intel reported CoW hybrid bonds with a 3-μm pitch, and, as talked about, a crew at Imec managed 2 μm, largely by making the transferred dies very flat whereas they had been nonetheless hooked up to the wafer and maintaining them additional clear all through the method. Each teams used plasma etching to cube up the dies as an alternative of the same old methodology, which makes use of a specialised blade. Not like a blade, plasma etching doesn’t result in chipping on the edges, which creates particles that might intrude with connections. It additionally allowed the Imec group to form the die, making chamfered corners that relieve mechanical stress that might break connections.
CoW hybrid bonding goes to be essential to the way forward for high-bandwidth reminiscence (HBM), in line with a number of researchers at ECTC. HBM is a stack of DRAM dies—at the moment 8 to 12 dies excessive—atop a control-logic chip. Usually positioned inside the identical bundle as high-end
GPUs, HBM is essential to dealing with the tsunami of knowledge wanted to run giant language fashions like ChatGPT. As we speak, HBM dies are stacked utilizing microbump expertise, so there are tiny balls of solder surrounded by an natural filler between every layer.
However with AI pushing reminiscence demand even larger, DRAM makers need to stack 20 layers or extra in HBM chips. The quantity that microbumps take up implies that these stacks will quickly be too tall to suit correctly within the bundle with GPUs. Hybrid bonding would shrink the peak of HBMs and in addition make it simpler to take away extra warmth from the bundle, as a result of there could be much less thermal resistance between its layers.
“I believe it’s attainable to make a more-than-20-layer stack utilizing this expertise.” —Hyeonmin Lee, Samsung
At ECTC, Samsung engineers confirmed that hybrid bonding may yield a 16-layer HBM stack. “I believe it’s attainable to make a more-than-20-layer stack utilizing this expertise,” says
Hyeonmin Lee, a senior engineer at Samsung. Different new CoW expertise may additionally assist deliver hybrid bonding to high-bandwidth reminiscence. Researchers at CEA Leti are exploring what’s often called self-alignment expertise, says Souriau. That might assist guarantee good CoW connections utilizing simply chemical processes. Some elements of every floor could be made hydrophobic and a few hydrophilic, leading to surfaces that might slide into place mechanically.
At ECTC, researchers from Tohoku College and Yamaha Robotics reported work on an identical scheme, utilizing the floor rigidity of water to align 5-μm pads on experimental DRAM chips with higher than 50-nm accuracy.
The Bounds of Hybrid Bonding
Researchers will nearly actually maintain decreasing the pitch of hybrid-bonding connections. A 200-nm WoW pitch isn’t just attainable however fascinating,
Han-Jong Chia, a undertaking supervisor for pathfinding methods at Taiwan Semiconductor Manufacturing Co. , instructed engineers at ECTC. Inside two years, TSMC plans to introduce a expertise known as bottom energy supply. (Intel plans the identical for the top of this 12 months.) That’s a expertise that places the chip’s chunky power-delivery interconnects under the floor of the silicon as an alternative of above it. With these energy conduits out of the way in which, the uppermost ranges can join higher to smaller hybrid-bonding bond pads, TSMC researchers calculate. Bottom energy supply with 200-nm bond pads would minimize down the capacitance of 3D connections a lot {that a} measure of power effectivity and sign velocity could be as a lot as eight instances higher than what might be achieved with 400-nm bond pads.
Chip-on-wafer hybrid bonding is extra helpful than wafer-on-wafer bonding, in that it could actually place dies of 1 measurement onto a wafer of bigger dies. Nonetheless, the density of connections that may be achieved is decrease than for wafer-on-wafer bonding.Imec
Sooner or later sooner or later, if bond pitches slender even additional, Chia suggests, it would change into sensible to “fold” blocks of circuitry so they’re constructed throughout two wafers. That approach a few of what at the moment are lengthy connections inside the block would possibly be capable of take a vertical shortcut, doubtlessly rushing computations and decreasing energy consumption.
And hybrid bonding might not be restricted to silicon. “As we speak there’s loads of improvement in silicon-to-silicon wafers, however we’re additionally trying to do hybrid bonding between gallium nitride and silicon wafers and glass wafers…every part on every part,” says CEA Leti’s Souriau. His group even introduced analysis on hybrid bonding for quantum-computing chips, which includes aligning and bonding superconducting niobium as an alternative of copper.
“It’s troublesome to say what the restrict can be,” Souriau says. “Issues are shifting very quick.”
This text was up to date on 11 August 2024.
This text seems within the September 2024 print difficulty.
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